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preliminary W78IE52 8-bit microcontroller publication release date: april 20, 2005 - 1 - revision a2 1. general description the W78IE52 is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. the instruction set for the W78IE52 is fully compatible with the standard 8051. the W78IE52 contains an 8k bytes flash eprom; a 256 bytes ram; four 8-bit bi-directional and bit- addressable i/o ports; an additional 4-bit i/o port p4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. these peripherals are supported by eight sources two-level interrupt capability. to facilitate programming and verificati on, the flash eprom inside the W78IE52 allows the program memory to be programmed and read electronica lly. once the code is confirmed, the user can protect the code for security. the W78IE52 microcontroller has two power reduct ion modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. 2. features ? fully static design 8-bit cmos microcontroller ? wide supply voltage of 2.4v to 5.5v ? industrial temperature grade -40 o c ? 85 o c ? 256 bytes of on-chip scratchpad ram ? 8 kb electrically erasable/programmable flash eprom ? 64 kb program memory address space ? 64 kb data memory address space ? four 8-bit bi-directional ports ? one extra 4-bit bit-addre ssable i/o port, additional int2 / int3 (available on 44-pin plcc package) ? three 16-bit timer/counters ? one full duplex serial port (uart) ? watchdog timer ? eight sources, two-level interrupt capability ? emi reduction mode ? built-in power management ? code protection mechanism ? packages: ? dip 40: W78IE52 ? plcc 44: W78IE52p comment [w1]:
preliminary W78IE52 - 2 - 3. pin configurations vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (W78IE52) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (W78IE52p) 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2
preliminary W78IE52 publication release date: april 20, 2005 - 3 - revision a2 4. pin description symbol descriptions e a external access enable : this pin forces the processor to execute out of external rom. it should be kept high to access internal ro m. the rom address and data will not be presented on the bus if e a pin is high and the program counter is within on-chip rom area. psen program store enable : psen enables the external rom data onto the port 0 address/ data bus during fetch and movc oper ations. when internal rom access is performed, no psen strobe signal outputs from this pin. ale address latch enable : ale is used to enable the address latch that separates the address from the data on port 0. rst reset : a high on this pin for two machine cycles while the oscillator is running resets the device. xtal1 crystal1 : this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 crystal2 : this is the crystal oscillator ou tput. it is the inversion of xtal1. v ss ground : ground potential v dd power supply : supply voltage for operation. p0.0 ? p0.7 port 0 : port 0 is a bi-directional i/o port whic h also provides a multiplexed low order address/data bus during accesses to external memory. the port 0 is also an open-drain port and external pull-ups need to be connected while in programming. p1.0 ? p1.7 port 1 : port 1 is a bi-directional i/o port with internal pull-ups. the bits have alternate functions which are described below: t2(p1.0): timer/counter 2 external count input t2ex(p1.1): timer/counter 2 reload/capture control p2.0 ? p2.7 port 2 : port 2 is a bi-directional i/o port with in ternal pull-ups. this port also provides the upper address bits for accesses to external memory. p3.0 ? p3.7 port 3 : port 3 is a bi-directional i/o port with internal pull-ups. all bits have alternate functions, which are described below: rxd(p3.0) : serial port receiver input txd(p3.1) : serial port transmitter output int0 (p3.2): external interrupt 0 int1 (p3.3): external interrupt 1 t0(p3.4) : timer 0 external input t1(p3.5) : timer 1 external input wr (p3.6) : external data memory write strobe rd (p3.7) : external data memory read strobe p4.0 ? p4.3 port 4: another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ).
preliminary W78IE52 - 4 - 5. block diagram p3.0 ~ p3.7 p1.0 ~ p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale vss vcc rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 256 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 ~ p4.3 port 4 port 0 port 2 p2.0 ~ p2.7 p0.0 ~ p0.7 int2 int3 watchdog timer rom 6. functional description the W78IE52 architecture consists of a core controller surrounded by various registers, five general purpose i/o ports, 256 bytes of ram, three timer/c ounters, and a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64k data storage space. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for time r 2. the tcon and tmod registers provide control functions for timers 0 and 1. the t2con re gister provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2.
preliminary W78IE52 publication release date: april 20, 2005 - 5 - revision a2 the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a special feature of the W78IE52: it is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. ti mer 2 has three operating modes: capture, auto- reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. new defined peripheral in order to be more suitable for i/o, an extra 4-bit bit-addressable port p4 and two external interrupt int2 , int3 has been added to either the plcc or qfp 44 pin package. and description follows: 1. int2 / int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb (/clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-leve l triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-leve l triggered when this bit is set/cleared by software interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3
preliminary W78IE52 - 6 - 2. port4 another bit-addressable port p4 is also available and only 4 bits (p4<3:0>) can be used. this port address is located at 0d8h with the same function as that of port p1, except the p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources ( int2 , int3 ). example: p4 reg 0d8h mov p4, #0ah ; output data "a" through p4.0 ? p4.3. mov a, p4 ; read p4 status to accumulator. orl p4, #00000001b anl p4, #11111110b 3. reduce emi emission because of on-chip flash eprom, when a program is running in internal rom space, the ale will be unused. the transition of ale will cause noise, so it can be turned off to reduce the emi emission if it is useless. turning off the ale signal transition on ly requires setting the bit 0 of the auxr sfr, which is located at 08eh. when ale is turned off, it will be reactivated when the program accesses external rom/ram data or jumps to execute an external rom code. the ale signal will turn off again after it has been completely accessed or the program returns to internal rom code space. the ao bit in the auxr register, when set, disables the ale output. in order to reduce emi emission from oscillation circuitry, W78IE52 allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the b7 bit of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscill ator amplifier, reducing a half of gain may affect the external crystal operat ing improperly at high frequency above 24 mhz. the value of r and c1, c2 may need some adjustment while running at lower gain. ***auxr - auxiliary register (8eh) - - - - - - - ao ao: turn off ale output. 4. power-off flag ***pcon - power control (87h) - - - pof gf1 gf0 pd idl pof: power off flag. bit is set by hardware when power on reset. it can be cleared by software to determine chip reset is a warm boot or cold boot. gf1, gf0: these two bits are general-purpose flag bits for the user. pd: power down mode bit. set it to enter power down mode. idl: idle mode bit. set it to enter idle mode. the power-off flag is located at pcon.4. this bit is set when v dd has been applied to the part. it can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
preliminary W78IE52 publication release date: april 20, 2005 - 7 - revision a2 watchdog timer the watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event time r. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time-out interval. when the time-out occurs a system reset can also be caused if it is enabled. the main use of the watchdog timer is as a system monitor. this is important in real-time contro l applications. in case of power glitches or electro- magnetic interference, the processor may begin to ex ecute errant code. if this is left unchecked the entire system may crash. the watchdog time-out sele ction will result in di fferent time-out values depending on the clock speed. the watchdog timer will de disabled on reset. in general, software should restart the watchdog timer to put it into a known state. the control bits that support the watchdog timer are discussed below. watchdog timer control register bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemonic: wdtc address: 8fh enw : enable watch-dog if set. clrw: clear watch-dog timer and prescaler if set. this flag will be cleared automatically widl : if this bit is set, watch-dog is enabled under idle mode. if cleared, watch-dog is disabled under idle mode. default is cleared. ps2, ps1, ps0: watch-dog prescaler timer select. prescaler is selected when set ps2 ? 0 as follows: ps2 ps1 ps0 prescaler select 0 0 0 2 0 1 0 4 0 0 1 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 the time-out period is obtained using the following equation: 1 osc 2 prescaler 1000 12 ms 14 before watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to wdtc.6 (clrw). after 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. the watchdog timer is cleared on reset.
preliminary W78IE52 - 8 - osc 1/12 prescaler 14-bit timer clear clrw external reset internal reset widl idle enw watchdog timer block diagram typical watch-dog time-out period when osc = 20 mhz ps2 ps1 ps0 watchdog time-out period 0 0 0 19.66 ms 0 1 0 39.32 ms 0 0 1 78.64 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s clock the W78IE52 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used. this ma kes the W78IE52 relatively insensitive to duty cycle variations in the clock. the W78IE52 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground. an external clock source should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. power management idle mode the idle mode is entered by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals an d the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode when the pd bit of the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks are stopped, incl uding the oscillator. the only way to exit power-down mode is by a reset.
preliminary W78IE52 publication release date: april 20, 2005 - 9 - revision a2 reset the external reset signal is sampl ed at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an in ternal trigger circuit in the reset line is used to deglitch the reset line when the W78IE52 is used with an external rc network. the reset logic also has a special glitch removal circuit t hat ignores glitches on the reset line. during reset, the ports are initialized to ffh, the st ack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. 7. on-chip flash eprom characteristics the W78IE52 has several modes to program the on-chip flash eprom. all these operations are configured by the pins rst, ale, psen , a9ctrl (p3.0), a13ctrl (p3.1), a14ctrl (p3.2), oectrl (p3.3), ce (p3.6), oe (p3.7), a0 (p1.0) and v pp ( e a ). moreover, the a15 ? a0 (p2.7 ? p2.0, p1.7 ? p1.0) and the d7 ? d0 (p0.7 ? p0.0) serve as the address and data bus respectively for these operations. read operation this operation is supported for customer to read thei r code and the security bits. the data will not be valid if the lock bit is programmed to low. output disable condition when the oe is set to high, no data output appears on the d7..d0. program operation this operation is used to program the data to flash eprom and the security bits. program operation is done when the v pp is reach to v cp (12.5v) level, ce set to low, and oe set to high. program verify operation all the programming data must be checked after program operations. this operation should be performed after each byte is programmed; it will ensure a substantial program margin. erase operation an erase operation is the only way to change data from 0 to 1. this operation will erase all the flash eprom cells and the security bits from 0 to 1. this erase operation is done when the v pp is reach to v ep level, ce set to low, and oe set to high. erase verify operation after an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. the erase verify operation automatically ensures a substantial erase margin. this operation will be done after the erase operation if v pp = v ep (14.5v), ce is high and oe is low.
preliminary W78IE52 - 10 - program/erase inhibit operation this operation allows parallel erasi ng or programming of multiple chips with different data. when p3.6 ( ce ) = v ih , p3.7 ( oe ) = v ih , erasing or programming of non-targeted chips is inhibited. so, except for the p3.6 and p3.7 pins, the individual chips may have common inputs. operations p3.0 (a9 ctrl) p3.1 (a13 ctrl) p3.2 (a14 ctrl) p3.3 (oe ctrl) p3.6 ( ce ) p3.7 ( oe ) e a (v pp ) p2, p1 (a15?a0) p0 ( d7?d0) notes read 0 0 0 0 0 0 1 address data out output disable 0 0 0 0 0 1 1 x hi-z program 0 0 0 0 0 1 v cp address data in program verify 0 0 0 0 1 0 v cp address data out 3 erase 1 0 0 0 0 1 v ep a0: 0, others: x data in 0ffh 4 erase verify 1 0 0 0 1 0 v ep address data out 5 program/eras e inhibit x 0 0 0 1 1 v cp / v ep x x notes: 1. all these operations happen in rst = v ih , ale = v il and psen = v ih . 2. v cp = 12.5v, v ep = 14.5v, v ih = v dd , v il = v ss . 3. the program verify operation fo llows behind the program operation. 4. this erase operation will erase all the on -chip flash eprom cells and the security bits. 5. the erase verify operation fo llows behind the erase operation. 8. security bits during the on-chip flash eprom operation m ode, the flash eprom can be programmed and verified repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and those operations on it are described below. the W78IE52 has a special setting register, the security register, which can not be accessed in normal mode. the security register can only be accessed from the flash eprom operation mode. those bits of the security registers can not be changed once they have been programmed from high to low. they can only be reset through erase-all operation. the security register is addressed in the flash eprom operation mode by address #0ffffh.
preliminary W78IE52 publication release date: april 20, 2005 - 11 - revision a2 b0 b1 b0 : lock bit, logic 0: active b1 : movc inhibit, logic 0: the movc instruction in external memory cannot access the code in internal memory. logic 1: no restriction. default 1 for all security bits. special setting register d7 d6 d5 d4 d3 d2 d1 d0 security bits 8kb flash eprom program memory reserved security register 0ffffh 0000h 1fffh reserved b2 b2 : encryption logic 0: the encryption logic enable logic 1: the encryption logic disable reserved bits must be kept in logic 1. b7 b7 : osillator control logic 0: 1/2 gain logic 1: full gain lock bit this bit is used to protect the customer's progr am code in the W78IE52. it may be set after the programmer finishes the programming and verifies sequence. once this bit is set to logic 0, both the flash eprom data and special setting registers can not be accessed again. movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can prevent the movc instruction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a movc instruction in internal program memory space will always be able to access the rom data in both in ternal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. encryption this bit is used to enable/disable the encryption logi c for code protection. once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. only whole chip erase will reset this bit.
preliminary W78IE52 - 12 - p1 p3.0 p3.1 p3.2 p3.3 p3.6 p3.7 x'tal1 x'tal2 p0 ea/vpp ale rst psen p2 vss a0 to a7 v cp v il v ih v il v il v il v il v il a8 to a15 pgm data v ih v ih +5v programming configuration p1 p3.0 p3.1 p3.2 p3.3 p3.6 p3.7 x'tal1 x'tal2 p0 ea/vpp ale rst psen p2 vss a0 to a7 v cp v il v ih v il v il v il v il v il a8 to a15 pgm data v ih v ih +5v programming verification v dd v dd 9. absolute maximum ratings parameter symbol min. max. unit dc power supply v dd ? v ss -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a -40 85 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affe ct the life and reliability of the device. 10. dc characteristics v ss = 0v, t a = 25 c, unless otherwise specified. parameter sym. specification unit test conditions min. max. operating voltage v dd 2.4 5.5 v operating current i dd - 20 ma no load v dd = 5.5v - 3 ma no load v dd = 2.4v idle current i idle - 6 ma v dd = 5.5v, f osc = 20 mhz - 1.5 ma v dd = 2.4v, f osc = 12 mhz power down current i pwdn - 50 a v dd = 5.5v, f osc = 20 mhz - 20 a v dd = 2.4v, f osc = 12 mhz input current p1, p2, p3, p4 i in1 -50 +10 a v dd = 5.5v v in = 0v or v dd input current rst i in2 -10 +300 a v dd = 5.5v 0 < v in < v dd
preliminary W78IE52 publication release date: april 20, 2005 - 13 - revision a2 dc characteristics, continued parameter sym. pecification unit test conditions min. max. input leakage current p0, ea i lk -10 +10 a v dd = 5.5v 0v < v in < v dd logic 1 to 0 transition current p1, p2, p3, p4 i tl [*4] -500 - a v dd = 5.5v v in = 2.0v input low voltage v il1 0 0.8 v v dd = 4.5v p0, p1, p2, p3, p4, e a 0 0.5 v v dd = 2.4v input low voltage v il2 0 0.8 v v dd = 4.5v rst[*1] 0 0.3 v v dd = 2.4v input low voltage v il3 0 0.8 v v dd = 4.5v xtal1 [*3] 0 0.6 v v dd = 2.4v input high voltage v ih1 2.4 v dd +0.2 v v dd = 5.5v p0, p1, p2, p3, p4, e a 1.4 v dd +0.2 v v dd = 2.4v input high voltage v ih2 3.5 v dd +0.2 v v dd = 5.5v rst[*1] 1.7 v dd +0.2 v v dd = 2.4v input high voltage v ih3 3.5 v dd +0.2 v v dd = 5.5v xtal1 [*3] 1.6 v dd +0.2 v v dd = 2.4v output low voltage v ol1 - 0.45 v v dd = 4.5v, i ol = +2 ma p1, p2, p3, p4 - 0.25 v v dd = 2.4v, i ol = +1 ma output low voltage v ol2 - 0.45 v v dd = 4.5v, i ol = +4 ma p0, ale, psen [*2] - 0.25 v v dd = 2.4v, i ol = +2 ma sink current i sk1 4 12 ma v dd = 4.5v, vin = 0.45v p1, p2, p3, p4 1.8 5.4 ma v dd = 2.4v, vin = 0.45v sink current i sk2 8 16 ma v dd = 4.5v, vin = 0.45v p0, ale, psen 4.0 9 ma v dd = 2.4v, vin = 0.45v output high voltage v oh1 2.4 - v v dd = 4.5v, i oh = -100 a p1, p2, p3, p4 1.4 - v v dd = 2.4v, i oh = -8 a output high voltage v oh2 2.4 - v v dd = 4.5v, i oh = -400 a p0, ale, psen [*2] 1.4 - v v dd = 2.4v, i oh = -200 a source current i sr1 -100 -250 a v dd = 4.5v, vin = 2.4v p1, p2, p3, p4 -10 -30 a v dd = 2.4v, vin = 1.4v source current i sr2 -8 -14 ma v dd = 4.5v, vin = 2.4v p0, ale, psen -1.0 -2.4 ma v dd = 2.4v, vin = 1.4v notes: *1. rst pin is a schmitt trigger input. *2. p0, ale and /psen are tested in the external access mode. *3. xtal1 is a cmos input. *4. pins of p1, p2, p3, p4 can source a transition curre nt when they are being externally driven from 1 to 0.
preliminary W78IE52 - 14 - 11. ac characteristics the ac specifications are a functi on of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the inter nal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.6micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed f op 0 - 24 mhz 1 clock period t cp 41.7 - - ns 2 clock high t ch 20 - - ns 3 clock low t cl 20 - - ns 3 notes: 1. the clock may be stopped indef initely in either state. 2. the t cp specification is used as a refe rence in other specifications. 3. there are no duty cycle r equirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - ? - - ns 4 address hold from ale low t aah 1 t cp - ? - - ns 1, 4 ale low to psen low t apl 1 t cp - ? - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - ? 2 t cp - ns 4 psen pulse width t psw 3 t cp - ? 3 t cp - ns 4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " ? " (due to buffer driving delay and wire loading) is 20 ns.
preliminary W78IE52 publication release date: april 20, 2005 - 15 - revision a2 data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - ? - 3 t cp + ? ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - ? 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " ? " (due to buffer driving delay and wire loading) is 20 ns. data write cycle parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - ? - 3 t cp + ? ns data valid to wr low t dad 1 t cp - ? - - ns data hold from wr high t dwd 1 t cp - ? - - ns wr pulse width t dwr 6 t cp - ? 6 t cp - ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t cp - - ns note: ports are read during s5p2, and output data becomes availabl e at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. program operation parameter symbol min. typ. max. unit v pp setup time t vps 2.0 - - s data setup time t ds 2.0 - - s data hold time t dh 2.0 - - s address setup time t as 2.0 - - s
preliminary W78IE52 - 16 - program operation, continued parameter symbol min. typ. max. unit address hold time t ah 0 - - s ce program pulse width for program operation t pwp 290 300 310 s oectrl setup time t ocs 2.0 - - s oectrl hold time t och 2.0 - - s oe setup time t oes 2.0 - - s oe high to output float t dfp 0 - 130 ns data valid from oe t oev - - 150 ns note: flash data can be accessed only in flash mode. the rst pin must pull in v ih status, the ale pin must pull in v il status, and the psen pin must pull in v ih status. 12. timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw
preliminary W78IE52 publication release date: april 20, 2005 - 17 - revision a2 timing waveforms, continued data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd
preliminary W78IE52 - 18 - timing waveforms, continued port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds program operation p2, p1 (a15... a0) address stable v ih v il address valid p3.6 (ce) v ih v il v ih v il v ih v il data in data out vpp d out read verify vcp v ih program program verify t vps t ds t dh t as t ah t pwp t oes t dfp t oev t ocs v ih v il t och p3.7 (oe) p0 (a7... a0) p3.3 (oectrl)
preliminary W78IE52 publication release date: april 20, 2005 - 19 - revision a2 13. typical application circuits expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 W78IE52 10 u 8.2 k dd crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 v dd v figure a crystal c1 c2 r 16 mhz 30p 30p - 24 mhz 15p 15p - above table shows the reference values for crystal applications (full gain). note: c1, c2, r components refer to figure a.
preliminary W78IE52 - 20 - typical application circuits, continued expanded external data memory and oscillator 10 u 8.2 k dd oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 1 2 3 4 5 6 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 W78IE52 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v figure b 14. package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2
preliminary W78IE52 publication release date: april 20, 2005 - 21 - revision a2 package dimensions, continued 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a e h e l y b c d a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
preliminary W78IE52 - 22 - revision history version date page description a1 september 14, 2001 - initial issued a2 april 20, 2005 22 add important notice important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atom ic energy control instruments, airplane or spaceship instrument s, transportation instru ments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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